| General information | |
|---|---|
| Launched | 2011 |
| Performance | |
| Max. CPU clock rate | 2.85 GHz to 3.0 GHz |
| Cache | |
| L1 cache | 8×(16+16) kB |
| L2 cache | 8×128 kB |
| L3 cache | 4 MB |
| Architecture and classification | |
| Technology node | 40 nm |
| Instruction set | SPARC V9 |
| Physical specifications | |
| Cores |
|
| Products, models, variants | |
| Core name |
|
| History | |
| Predecessor | SPARC T3 |
| Successor | SPARC T5 |
The SPARC T4 is a SPARC multicore microprocessor introduced in 2011 by Oracle Corporation. The processor is designed to offer high multithreaded performance (8 threads per core, with 8 cores per chip), as well as high single threaded performance from the same chip.[1] The chip is the 4th generation[2] processor in the T-Series family. Sun Microsystems brought the first T-Series processor (UltraSPARC T1) to market in 2005.
The chip is the first Sun/Oracle SPARC chip to use dynamic threading[3] and out-of-order execution.[4] It incorporates one floating point unit and one dedicated cryptographic unit per core.[2] The cores use the 64-bit SPARC Version 9 architecture running at frequencies between 2.85 GHz and 3.0 GHz, and are built in a 40 nm process with a die size of 403 mm2 (0.625 sq in).[1]
- ^ a b SPARC T4 Processor Data(archived) Sheet (PDF), Oracle Corporation, archived from the original (PDF) on 2012-05-16
- ^ a b Jean S. Bozman; Matthew Eastwood (April 2012), SPARC Servers: An Effective Choice for Efficiency in the Datacenter, p. 9 (PDF), IDC
- ^ Timothy Prickett Morgan (27 September 2011), "Oracle rises for Unix server push", www.theregister.co.uk, The Register, pp. 1–2
- ^ Manish Shah; Robert Golla; Gregory Grohoski; Paul Jordan; Jama Barreh; Jeff Brooks; Mark Greenberg; Gideon Levinsky; Mark Luttrell; Christopher Olson; Zeid Samoail; Matt Smittle; Tom Ziaja (March–April 2012), IEEE Micro, vol. 32, no. 2, Sparc T4: A Dynamically Threaded Server-on-a-Chip, pp. 8-19, IEEE Computer Society